ia-32_instruction-set-ref_a-m

Mode 3 388 vol 2 instruction set reference a m 64 bit

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Unformatted text preview: n, or P6 family processor. Operation DEST[FPUControlWord] FPUControlWord; DEST[FPUStatusWord] FPUStatusWord; DEST[FPUTagWord] FPUTagWord; DEST[FPUDataPointer] FPUDataPointer; DEST[FPUInstructionPointer] FPUInstructionPointer; DEST[FPULastInstructionOpcode] FPULastInstructionOpcode; FPU Flags Affected The C0, C1, C2, and C3 are undefined. Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-391 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-392 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSTSW/FNSTSW--Store x87 FPU Status Word Opcode 9B DD /7 Instruction FSTSW m2byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Store FPU status word at m2byte after checking for pending unmasked floatingpoint exceptions. Store FPU status word in AX register after checking for pending unmasked floatingpoint exceptions. Store FPU status word at m2byte without checking for pending unmasked floatingpoint exceptions. Store FPU status word in AX register without checking for pending unmasked floatingpoint exceptions. 9B DF E0 FSTSW AX Valid Valid DD /7 FNSTSW* m2byte Valid Valid DF E0 FNSTSW* AX Valid Valid NOTES: * See IA-32 Architecture Compatibility section below. Description Stores the current value of the x87 FPU status word in the destination location. The destination operand can be either a two-byte memory location or the AX register. The FSTSW instruction checks for and handles pen...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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