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Mode exceptions nm mf cr0embit 2 or cr0tsbit 3 1

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Unformatted text preview: s in Protected Mode. 3-412 Vol. 2 INSTRUCTION SET REFERENCE, A-M FXRSTOR--Restore x87 FPU, MMX Technology, SSE, SSE2, and SSE3 State Opcode 0F AE /1 Instruction FXRSTOR m512byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Restore the x87 FPU, MMX, XMM, and MXCSR register state from m512byte. Description Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in the source operand. This data should have been written to memory previously using the FXSAVE instruction, and in the same format as required by the operating modes. The first byte of the data should be located on a 16-byte boundary. There are three distinct layout of the FXSAVE state map: one for legacy and compatibility mode, a second format for 64-bit mode with promoted operandsize, and the third format is for 64-bit mode with default operand size. Table 3-48 shows the layout of the legacy/compatibility mode state information in memory and describes the fields in the memory image for the FXRSTOR and FXSAVE instructions. Table 3-51 shows the layout of the 64-bit mode stat information when REX.W is set. Table 3-52 shows the layout of the 64-bit mode stat information when REX.W is clear. The state image referenced with an FXRSTOR instruction must have been saved using an FXSAVE instruction or be in the same format as required by Table 3-48, Table 3-51, or Table 3-52. Referencing a state image saved with an FSAVE, FNSAVE instruction or incompatible field layout will result in an incorrect state restoration. The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and raise exceptions when loading x87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction. If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not restore the states of the XMM and MXCSR registers. This behavior is implementation dependent. If the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register with the FXRSTOR instruction will not result in a SIMD floating-point error condition being generated. Only the next occurrence of this unmasked exception will result in the exception being generated. Bit 6 and bits 16 through 32 of the MXCSR register are defined as reserved and should be set to 0. Attempting to write a 1 in any of these bits from the saved state image will result in a general protection exception (#GP) being generated. Operation (x87 FPU, MMX, XMM7-XMM0, MXCSR) Load(SRC); Vol. 2 3-413 INSTRUCTION SET REFERENCE, A-M x87 FPU and SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.) #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] =...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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