ia-32_instruction-set-ref_a-m

Mode exceptions nm ud if cr0tsbit 3 1 if cr0embit

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Unformatted text preview: int values from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be an XMM register or a 64-bit memory location. This instruction allows two single-precision floating-point values to be moved to and from the high quadword of an XMM register and memory. It cannot be used for register to register or memory to memory moves. When the destination operand is an XMM register, the low quadword of the register remains unchanged. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation MOVHPD instruction for memory to XMM move: DEST[127:64] SRC; (* DEST[63:0] unchanged *) MOVHPD instruction for XMM to memory move: DEST SRC[127:64]; Intel C/C++ Compiler Intrinsic Equivalent MOVHPS MOVHPS __m128d _mm_loadh_pi ( __m128d a, __m64 *p) void _mm_storeh_pi (__m64 *p, __m128d a) SIMD Floating-Point Exceptions None. Vol. 2 3-623 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-624 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-625 INSTRUCTION SET REFERENCE, A-M MOVLHPS--Move Packed Single-Precision Floating-Point Values Low to High Opcode OF 16 /r Instruction MOVLHPS xmm1, xmm2 64Bit Mode Valid Compat/ Leg Mode Valid Description Move two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1. Description Moves two packed single-precision floating-point values from the low quadword of the source operand (second operand) to the high quadword of the destination operand (first operand). The low quadword of the destination operand is left unchanged. In 64-bit mode, use of the REX.R prefix pe...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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