ia-32_instruction-set-ref_a-m

Mode exceptions same exceptions as in protected mode

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Unformatted text preview: mpare imm8 with r/m64. Compare r8 with r/m8. Compare r8 with r/m8. Compare r16 with r/m16. Compare r32 with r/m32. Compare r64 with r/m64. Compare r/m8 with r8. Compare r/m8 with r8. Compare r/m16 with r16. Compare r/m32 with r32. Compare r/m64 with r64. 80 /7 ib REX + 80 /7 ib 81 /7 iw 81 /7 id REX.W + 81 /7 id Valid Valid Valid Valid Valid Valid N.E. Valid Valid N.E. 83 /7 ib 83 /7 ib REX.W + 83 /7 ib 38 /r REX + 38 /r 39 /r 39 /r REX.W + 39 /r 3A /r REX + 3A /r 3B /r 3B /r REX.W + 3B /r Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid N.E. Valid N.E. Valid Valid N.E. Valid N.E. Valid Valid N.E. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. 3-122 Vol. 2 INSTRUCTION SET REFERENCE, A-M Description Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand. The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction. Appendix B, "EFLAGS Condition Codes," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, shows the relationship of the status flags and the condition codes. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation temp SRC1 - SignExtend(SRC2); ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*) Flags Affected The CF, OF, SF, ZF, AF, and PF flags are set according to the result. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Vol. 2 3-123 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an...
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