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Unformatted text preview: de Exceptions
#GP(0) #SS(0) #PF(fault-code) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
#SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-672 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVUPD--Move Unaligned Packed Double-Precision Floating-Point Values
64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F 10 /r Instruction MOVUPD xmm1, xmm2/m128 MOVUPD xmm2/m128, xmm 66 0F 11 /r Valid Valid Description Move packed double-precision floating-point values from xmm2/m128 to xmm1. Move packed double-precision floating-point values from xmm1 to xmm2/m128. Description
Moves a double quadword containing two packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, store the contents of an XMM register into a 128-bit memory location, or move data between two XMM registers. When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte boundary without causing a general-protection exception (#GP) to be generated. To move double-precision floating-point values to and from memory locations that are known to be aligned on 16-byte boundaries, use the MOVAPD instruction. While executing in 16-bit addressing mode, a linear address for a 128-bit data access that overlaps the end of a 16-bit segment is not allowed and is defined as reserved behavior. A specific processor implementation may or may not generate a generalprotection exception (#GP) in this situation, and the address that spans the end of the segment may or may not wrap around to the beginning of the segment. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
DEST SRC; Intel C/C++ Compiler Intrinsic Equivalent
MOVUPD MOVUPD __m128 _mm_loadu_pd(double * p) void_mm_storeu_pd(double *p, __m128 a) SIMD Floating-Point Exceptions
None. Vol. 2 3-673 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions
#AC(0) #GP(0) #SS(0) #PF(fault-code) #NM #UD If alignment checking is enabled and an unaligned memory reference is made. For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions
#AC(0) GP(0) #NM #UD If alignment checking is enabled and an unaligned memory refere...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11