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Unformatted text preview: uction to 64-bit operands. See the summary chart at the beginning of this section for encoding data and limits. Operation
DEST SRC; DEST SRC; DEST SRC; DEST SRC; IF DEST = r32 THEN DEST[31:4] ZeroExtend; ELSE DEST[63:4] ZeroExtend; FI; Intel C/C++ Compiler Intrinsic Equivalent
int_mm_movemask_ps(__m128 a) SIMD Floating-Point Exceptions
None. 3-634 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions
#NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions
Same exceptions as in Protected Mode. Virtual 8086 Mode Exceptions
Same exceptions as in Protected Mode. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
Same exceptions as in Protected Mode. Vol. 2 3-635 INSTRUCTION SET REFERENCE, A-M MOVNTDQ--Store Double Quadword Using Non-Temporal Hint
64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F E7 /r Instruction MOVNTDQ m128, xmm Description Move double quadword from xmm to m128 using nontemporal hint. Description
Moves the double quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, which is assumed to contain integer data (packed bytes, words, doublewords, or quadwords). The destination operand is a 128-bit memory location. The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see "Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1. Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTDQ instructions if multiple processors might use different memory types to read/write the destination memory locations. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
DEST SRC; Intel C/C++ Compiler Intrinsic Equivalent
MOVNTDQ void_mm_stream_si128 ( __m128i *p, __m128i a) SIMD Floating-Point Exceptions
None. 3-636 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11