Nm xm ud if any part of the operand lies outside the

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-574 Vol. 2 INSTRUCTION SET REFERENCE, A-M MFENCE--Memory Fence Opcode 0F AE /6 Instructio n MFENCE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Serializes load and store operations. Description Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes in program order the MFENCE instruction is globally visible before any load or store instruction that follows the MFENCE instruction is globally visible. The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any SFENCE and LFENCE instructions, and any serializing instructions (such as the CPUID instruction). Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store ordering between routines that produce weaklyordered results and routines that consume that data. It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the MFENCE instruction is not ordered with respect to PREFETCHh instructions or any other speculative fetching mechanism (that is, data could be speculatively loaded into the cache just before, during, or after the execution of an MFENCE instruction). This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation Wait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible); Intel C/C++ Compiler Intrinsic Equivalent void_mm_mfence(void) Exceptions (All Modes of Operation) None. Vol. 2 3-575 INSTRUCTION SET REFERENCE, A-M MINPD--Return Minimum Packed Double-Precision Floating-Point Values Opcode 66 0F 5D /r Instruction MINPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the minimum doubleprecision floatin...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online