ia-32_instruction-set-ref_a-m

P6 family processors cr0et remains set after any load

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Unformatted text preview: n real-address mode. When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and DR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in an undefined opcode (#UD) exception. (The CR4 register was added to the IA-32 Architecture beginning with the Pentium processor.) At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read. The two bits in the mod field are always 11. The r/m field specifies the general-purpose register loaded or read. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation IF ((DE = 1) and (SRC or DEST = DR4 or DR5)) THEN #UD; ELSE DEST SRC; FI; 3-600 Vol. 2 INSTRUCTION SET REFERENCE, A-M Flags Affected The OF, SF, ZF, AF, PF, and CF flags are undefined. Protected Mode Exceptions #GP(0) #UD #DB If the current privilege level is not 0. If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. If any debug register is accessed while the DR7.GD[bit 13] = 1. Real-Address Mode Exceptions #UD #DB If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. If any debug register is accessed while the DR7.GD[bit 13] = 1. Virtual-8086 Mode Exceptions #GP(0) The debug registers cannot be loaded or read when in virtual8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) #UD #DB If the current privilege level is not 0. If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. If any debug register is accessed while the DR7.GD[bit 13] = 1. Vol. 2 3-601 INSTRUCTION SET REFERENCE, A-M MOVAPD--Move Aligned Packed Double-Precision Floating-Point Values Opcode 66 0F 28 /r 66 0F 29 /r Instruction MOVAPD xmm1, xmm2/m128 MOVAPD xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move packed double-precision floating-point values from xmm2/m128 to xmm1. Move packed double-precision floating-point values from xmm1 to xmm2/m128. Valid Valid Description Moves a double quadword containing two packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generat...
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