ia-32_instruction-set-ref_a-m

Set reference a m real address mode exceptions gp0 if

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Unformatted text preview: [bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-56 Vol. 2 INSTRUCTION SET REFERENCE, A-M ANDPS--Bitwise Logical AND of Packed Single-Precision Floating-Point Values Opcode 0F 54 /r Instruction ANDPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[127:0] DEST[127:0] BitwiseAND SRC[127:0]; Intel C/C++ Compiler Intrinsic Equivalent ANDPS __m128 _mm_and_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol. 2 3-57 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #UD For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. 3-58 Vol. 2 INSTRUCTION SET REFERENCE, A-M ANDNPD--Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values Opcode 66 0F 55 /r Instruction ANDNPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND NOT of xmm2/m128 and xmm1. Description Inverts the bits of the two packed double-precision floating-point values in the destination operand (first operand), performs a bitwise logical AND of the two packed double-precision floating-point values in the source operand (second operand) and the temporary inverted result, and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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