ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: floating-point operation. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] DEST[63:0] / SRC[63:0]; (* DEST[127:64] unchanged *) Intel C/C++ Compiler Intrinsic Equivalent DIVSD __m128d _mm_div_sd (m128d a, m128d b) SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. 3-272 Vol. 2 INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-273 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-274 Vol. 2 INSTRUCTION SET REFERENCE, A-M DIVSS--Divide Scalar Single-Precision Floating-Point Values Opcode F3 0F 5E /r Instruction DIVSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Divide low single-precision floatingpoint value in xmm1 by low singleprecision floating-point value in xmm2/m32. Description Divides the low single-precision floating-point value in the destination operand (first operand) by the low single-precision floating-point value in the source operand (second operand), and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination op...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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