ia-32_instruction-set-ref_a-m

Sf and zf and perform a move operation if the flags

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Unformatted text preview: ors. Software can determine if the CMOVcc instructions are supported by checking the processor's feature information with the CPUID instruction (see "CPUID--CPU Identification" in this chapter). In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Vol. 2 3-119 INSTRUCTION SET REFERENCE, A-M Operation temp SRC IF (64-Bit Mode) THEN IF condition TRUE THEN IF (OperandSize = 64) THEN DEST temp; ELSE DEST temp AND 0x00000000_FFFFFFFF; FI; FI; ELSE IF condition TRUE THEN DEST temp; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. 3-120 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-121 INSTRUCTION SET REFERENCE, A-M CMP--Compare Two Operands Opcode 3C ib 3D iw 3D id REX.W + 3D id Instruction CMP AL, imm8 CMP AX, imm16 CMP EAX, imm32 CMP RAX, imm32 CMP r/m8, imm8 CMP r/m8*, imm8 CMP r/m16, imm16 CMP r/m32, imm32 CMP r/m64, imm32 CMP r/m16, imm8 CMP r/m32, imm8 CMP r/m64, imm8 CMP r/m8, r8 CMP r/m8*, r8* CMP r/m16, r16 CMP r/m32, r32 CMP r/m64,r64 CMP r8, r/m8 CMP r8*, r/m8* CMP r16, r/m16 CMP r32, r/m32 CMP r64, r/m64 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. Description Compare imm8 with AL. Compare imm16 with AX. Compare imm32 with EAX. Compare imm32 signextended to 64-bits with RAX. Compare imm8 with r/m8. Compare imm8 with r/m8. Compare imm16 with r/m16. Compare imm32 with r/m32. Compare imm32 signextended to 64-bits with r/m64. Compare imm8 with r/m16. Compare imm8 with r/m32. Co...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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