ia-32_instruction-set-ref_a-m

Ss0 gp0 pffault code nm if alignment checking is

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Unformatted text preview: ive address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-680 Vol. 2 INSTRUCTION SET REFERENCE, A-M MUL--Unsigned Multiply 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid Valid N.E. Opcode F6 /4 REX + F6 /4 F7 /4 F7 /4 REX.W + F7 /4 Instruction MUL r/m8 MUL r/m8* MUL r/m16 MUL r/m32 MUL r/m64 Description Unsigned multiply (AX AL r/m8). Unsigned multiply (AX AL r/m8). Unsigned multiply (DX:AX AX r/m16). Unsigned multiply (EDX:EAX EAX r/m32). Unsigned multiply (RDX:RAX RAX r/m64. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand is an implied operand located in register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose register or a memory location. The action of this instruction and the location of the result depends on the opcode and the operand size as shown in Table 3-61. The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size), with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of the product are 0, the CF and OF flags are cleared; otherwise, the flags are set. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Table 3-61. MUL Results Operand Size Byte Word Doubleword Quadword AL AX EAX RAX Source 1 r/m8 r/m16 r/m32 r/m64 Source 2 AX DX:AX EDX:EAX RDX:RAX Destination Vol. 2 3-681 INSTRUCTION SET REFERENCE, A-M Operation IF (Byte operation) THEN AX AL SRC; ELSE (* Word or doubleword operation *) IF OperandSize = 16 THEN DX:AX AX SRC; ELSE IF OperandSize = 32 THEN EDX:EAX EAX SRC; FI; ELSE (* OperandSize = 64 *) RDX:RAX RAX SRC; FI; FI; Flags Affected The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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