ia-32_instruction-set-ref_a-m

See chapter 6 in intel 64 and ia 32 architectures

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Unformatted text preview: CPL or call gate DPL < call gate segment-selector RPL THEN #GP(call gate selector); FI; IF call gate not present THEN #NP(call gate selector); FI; IF call gate code-segment selector is NULL THEN #GP(0); FI; IF call gate code-segment selector index outside descriptor table limits THEN #GP(code segment selector); FI; 3-506 Vol. 2 INSTRUCTION SET REFERENCE, A-M Read code segment descriptor; IF code-segment segment descriptor does not indicate a code segment or code-segment segment descriptor is conforming and DPL > CPL or code-segment segment descriptor is non-conforming and DPL CPL THEN #GP(code segment selector); FI; IF IA32_EFER.LMA = 1 and (code-segment descriptor is not a 64-bit code segment or code-segment segment descriptor has both L-Bit and D-bit set) THEN #GP(code segment selector); FI; IF code segment is not present THEN #NP(code-segment selector); FI; IF instruction pointer is not within code-segment limit THEN #GP(0); FI; tempEIP DEST(Offset); IF GateSize = 16 THEN tempEIP tempEIP AND 0000FFFFH; FI; IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode) AND tempEIP outside code segment limit THEN #GP(0); FI CS DEST[SegmentSelector); (* Segment descriptor information also loaded *) CS(RPL) CPL; EIP tempEIP; END; TASK-GATE: IF task gate DPL < CPL or task gate DPL < task gate segment-selector RPL THEN #GP(task gate selector); FI; IF task gate not present THEN #NP(gate selector); FI; Read the TSS segment selector in the task-gate descriptor; IF TSS segment selector local/global bit is set to local or index not within GDT limits or TSS descriptor specifies that the TSS is busy THEN #GP(TSS selector); FI; IF TSS not present THEN #NP(TSS selector); FI; SWITCH-TASKS to TSS; IF EIP not within code segment limit THEN #GP(0); FI; END; TASK-STATE-SEGMENT: IF TSS DPL < CPL or TSS DPL < TSS segment-selector RPL or TSS descriptor indicates TSS not available THEN #GP(TSS selector); FI; Vol. 2 3-507 INSTRUCTION SET REFERENCE, A-M IF TSS is not present THEN #NP(TSS selector); FI; SWITCH-TASKS to TSS; IF EIP not within code segment limit THEN #GP(0); FI; END; Flags Affected All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur. Protected Mode Exceptions #GP(0) If offset in target operand, call gate, or TSS is beyond the code segment limits. If the segment selector in the destination operand, call gate, task gate, or TSS is NULL. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #GP(selector) If the segment selector index is outside descriptor table limits. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task state segment. If the DPL for a nonconforming-code segment is not equal to the CPL (When not using a call gate.) I...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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