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Size 32 action performed 32 bit effective address is

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Unformatted text preview: e address space from 0 to FFFFH. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #AC(0) If the memory address is in a non-canonical form. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-532 Vol. 2 INSTRUCTION SET REFERENCE, A-M LFENCE--Load Fence Opcode 0F AE /5 Instruction LFENCE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Serializes load operations. Description Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction. This serializing operation guarantees that every load instruction that precedes in program order the LFENCE instruction is globally visible before any load instruction that follows the LFENCE instruction is globally visible. The LFENCE instruction is ordered with respect to load instructions, other LFENCE instructions, any MFENCE instructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to store instructions or the SFENCE instruction. Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE instruction provides a performance-efficient way of insuring load ordering between routines that produce weakly-ordered results and routines that consume that data. It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the LFENCE instruction is not ordered with respect to PREFETCHh instructions or any other speculative fetching mechanism (that is, data could be speculative loaded into the cache just before, during, or after the execution of an LFENCE instruction). This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation Wait_On_Following_Loads_Until(preceding_loads_globally_visible); Intel C/C++ Compiler Intrinsic Equivalent void_mm_lfence(void) Exceptions (All Modes of Operation) None. Vol. 2 3-533 INSTRUCTION SET REFERENCE, A-M LGDT/LIDT--Load Global/Interrupt Descriptor Table Register Opcode 0F 01 /2 0F 01 /3 0F 01 /2 0F 01 /3 Instruction LGDT m16&32 LIDT m16&32 LGDT m16&64 LIDT m16&64 64-Bit Mode N.E. N.E. Valid Valid Compat/ Leg Mode Valid Valid N.E. N.E. Description Load m into GDTR. Load m into IDTR. Load m into GDTR. Load m into IDTR. Description Loads the values in...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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