ia-32_instruction-set-ref_a-m

Sreg a segment register the segment register bit

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Unformatted text preview: from the top of the FPU register stack (i 0 through 7). mm -- An MMX register. The 64-bit MMX registers are: MM0 through MM7. mm/m32 -- The low order 32 bits of an MMX register or a 32-bit memory operand. The 64-bit MMX registers are: MM0 through MM7. The contents of memory are found at the address provided by the effective address computation. mm/m64 -- An MMX register or a 64-bit memory operand. The 64-bit MMX registers are: MM0 through MM7. The contents of memory are found at the address provided by the effective address computation. xmm -- An XMM register. The 128-bit XMM registers are: XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. xmm/m32-- An XMM register or a 32-bit memory operand. The 128-bit XMM registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation. xmm/m64 -- An XMM register or a 64-bit memory operand. The 128-bit SIMD floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation. xmm/m128 -- An XMM register or a 128-bit memory operand. The 128-bit XMM registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation. 3-6 Vol. 2 INSTRUCTION SET REFERENCE, A-M 3.1.1.3 64-bit Mode Column in the Instruction Summary Table The "64-bit Mode" column indicates whether the opcode sequence is supported in 64-bit mode. The column uses the following notation: Valid -- Supported. Invalid -- Not supported. N.E. -- Indicates an instruction syntax is not encodable in 64-bit mode (it may represent part of a sequence of valid instructions in other modes). N.P. -- Indicates the REX prefix does not affect the legacy instruction in 64-bit mode. N.I. -- Indicates the opcode is treated as a new instruction in 64-bit mode. N.S. -- Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. 3.1.1.4 Compatibility/Legacy Mode Column in the Instruction Summary Table The "Compatibility/Legacy Mode" column provides information on the opcode sequence in either the compatibility mode or other IA-32 modes. The column uses the following notation: Valid -- Supported. Invalid -- Not supported. N.E. -- Indicates an Intel 64 instruction mnemonics/syntax that is not encodable; the opcode sequence is not applicable as an individual instruction in compatibility mode or IA-32 mode. The opcode may represent a valid sequence of legacy IA-32 instructions. 3.1.1.5 Description Column in the Instruction Summary Table The "Description" column briefly explains forms of the instruction. 3.1.1.6 Descripti...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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