Unformatted text preview: r vice versa. The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP. The FIDIV instructions convert an integer source operand to double extended-precision floating-point format before performing the division. When the source operand is an integer 0, it is treated as a +0. 3-314 Vol. 2 INSTRUCTION SET REFERENCE, A-M If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-29. FDIV/FDIVP/FIDIV Results
DEST - - -F -I SRC -0 +0 +I +F + NaN * + + + - - - * NaN -F +0 +F +F ** ** -F -F -0 NaN -0 +0 +0 +0 * * -0 -0 -0 NaN +0 -0 -0 -0 * * +0 +0 +0 NaN +F -0 -F -F ** ** +F +F +0 NaN + * - - - + + + * NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NOTES: F Means finite floating-point value. I Means integer. * Indicates floating-point invalid-arithmetic-operand (#IA) exception. ** Indicates floating-point zero-divide (#Z) exception. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation
IF SRC = 0 THEN #Z; ELSE IF Instruction is FIDIV THEN DEST DEST / ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* Source operand is floating-point value *) DEST DEST / SRC; FI; FI; Vol. 2 3-315 INSTRUCTION SET REFERENCE, A-M IF Instruction = FDIVP THEN PopRegisterStack; FI; FPU Flags Affected
C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions
#IS #IA #D #Z #U #O #P Stack underflow occurred. Operand is an SNaN value or unsupported format. / ; 0 / 0 Source is a denormal value. DEST / 0, where DEST is not equal to 0. Result is too small for destination format. Result is too large for destination format. Value cannot be represented exactly in destination format. Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions
#GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2]...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11