ia-32_instruction-set-ref_a-m

Top 1 st0 converttodoubleextendedprecisionfpsrc fpu

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Unformatted text preview: res 10 bytes of space in memory. The following table shows the results obtained when storing various classes of numbers in packed BCD format. Table 3-24. FBSTP Results ST(0) - or Value Too Large for DEST Format F -1 DEST * -D -1 < F < -0 -0 ** -0 +0 ** +D * * +0 +0 < F < +1 F +1 + or Value Too Large for DEST Format NaN NOTES: F Means finite floating-point value. D Means packed-BCD number. * Indicates floating-point invalid-operation (#IA) exception. ** 0 or 1, depending on the rounding mode. If the converted value is too large for the destination format, or if the source operand is an , SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is not masked, an invalid- 3-294 Vol. 2 INSTRUCTION SET REFERENCE, A-M arithmetic-operand exception (#IA) is generated and no value is stored in the destination operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation DEST BCD(ST(0)); PopRegisterStack; FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions #IS #IA Stack underflow occurred. Converted value that exceeds 18 BCD digits in length. Source operand is an SNaN, QNaN, , or in an unsupported format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #GP(0) If a segment register is being loaded with a segment selector that points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. Vol. 2 3-295 INSTRUCTION SET REFERENCE, A-M #SS #NM If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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