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Unformatted text preview: to a QNaN. Note that the processor does not implement the greater-than, greater-than-orequal, not-greater-than, and not-greater-than-or-equal relations. These comparisons can be made either by using the inverse relationship (that is, use the "not-lessthan-or-equal" to make a "greater-than" comparison) or by using software emulation. When using software emulation, the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in Table 3-7 under the heading Emulation. Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPD instruction. See Table 3-7.
: Table 3-8. Pseudo-Op and CMPPD Implementation
Pseudo-Op CMPEQPD xmm1, xmm2 CMPLTPD xmm1, xmm2 CMPLEPD xmm1, xmm2 CMPUNORDPD xmm1, xmm2 CMPNEQPD xmm1, xmm2 CMPNLTPD xmm1, xmm2 CMPNLEPD xmm1, xmm2 CMPPD Implementation CMPPD xmm1, xmm2, 0 CMPPD xmm1, xmm2, 1 CMPPD xmm1, xmm2, 2 CMPPD xmm1, xmm2, 3 CMPPD xmm1, xmm2, 4 CMPPD xmm1, xmm2, 5 CMPPD xmm1, xmm2, 6 3-126 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-8. Pseudo-Op and CMPPD Implementation
Pseudo-Op CMPORDPD xmm1, xmm2 CMPPD Implementation CMPPD xmm1, xmm2, 7 The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.) In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
CASE (COMPARISON PREDICATE) OF 0: OP EQ; 1: OP LT; 2: OP LE; 3: OP UNORD; 4: OP NEQ; 5: OP NLT; 6: OP NLE; 7: OP ORD; DEFAULT: Reserved; CMP0 DEST[63:0] OP SRC[63:0]; CMP1 DEST[127:64] OP SRC[127:64]; IF CMP0 = TRUE THEN DEST[63:0] FFFFFFFFFFFFFFFFH; ELSE DEST[63:0] 0000000000000000H; FI; IF CMP1 = TRUE THEN DEST[127:64] FFFFFFFFFFFFFFFFH; ELSE DEST[127:64] 0000000000000000H; FI; Intel C/C++ Compiler Intrinsic Equivalents
CMPPD for equality CMPPD for less-than CMPPD for less-than-or-equal CMPPD for greater-than CMPPD for greater-than-or-equal CMPPD for inequality CMPPD for not-less-than __m128d _mm_cmpeq_pd(__m128d a, __m128d b) __m128d _mm_cmplt_pd(__m128d a, __m128d b) __m128d _mm_cmple_pd(__m128d a, __m128d b) __m128d _mm_cmpgt_pd(__m128d a, __m128d b) __m128d _mm_cmpge_pd(__m128d a, __m128d b) __m128d _mm_cmpneq_pd(__m128d a, __m128d b) __m128d _mm_cmpnlt_pd(__m128d a, __m128d b) Vol. 2 3-127 INSTRUCTION SET REFERENCE, A-M CMPPD for not-greater-than CMPPD for not-greater-than-or-equal CMPPD for ordered CMPPD for unordered CMPPD for not-less-than-or-equal __m128d _mm_cmpngt_pd(__m128d a, __m128d b) __m128d _mm_cmpnge_...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11