ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 3-7 can be achieved only through software emulation. For these comparisons the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination operand), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in Table 3-7 under the heading Emulation. Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPSD instruction. See Table 3-10. 3-140 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-10. Pseudo-Ops and CMPSD Pseudo-Op CMPEQSD xmm1, xmm2 CMPLTSD xmm1, xmm2 CMPLESD xmm1, xmm2 CMPUNORDSD xmm1, xmm2 CMPNEQSD xmm1, xmm2 CMPNLTSD xmm1, xmm2 CMPNLESD xmm1, xmm2 CMPORDSD xmm1, xmm2 Implementation CMPSD xmm1,xmm2, 0 CMPSD xmm1,xmm2, 1 CMPSD xmm1,xmm2, 2 CMPSD xmm1,xmm2, 3 CMPSD xmm1,xmm2, 4 CMPSD xmm1,xmm2, 5 CMPSD xmm1,xmm2, 6 CMPSD xmm1,xmm2, 7 The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.) In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation CASE (COMPARISON PREDICATE) OF 0: OP EQ; 1: OP LT; 2: OP LE; 3: OP UNORD; 4: OP NEQ; 5: OP NLT; 6: OP NLE; 7: OP ORD; DEFAULT: Reserved; CMP0 DEST[63:0] OP SRC[63:0]; IF CMP0 = TRUE THEN DEST[63:0] FFFFFFFFFFFFFFFFH; ELSE DEST[63:0] 0000000000000000H; FI; (* DEST[127:64] unchanged *) Vol. 2 3-141 INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalents CMPSD for equality CMPSD for less-than CMPSD for less-than-or-equal CMPSD for greater-than CMPSD for greater-than-or-equal CMPSD for inequality CMPSD for not-less-than CMPSD for not-greater-than CMPSD for ordered CMPSD for unordered CMPSD for not-less-than-or-equal __m128d _mm_cmpeq_sd(__m128d a, __m128d b) __m128d _mm_cmplt_sd(__m128d a, __m128d b) __m128d _mm_cmple_sd(__m128d a, __m128d b) __m128d _mm_cmpgt_sd(__m128d a, __m128d b) __m128d _mm_cmpge_sd(__m128d a, __m128d b) __m128d _mm_cmpneq_sd(__m128d a, __m128d b) __m128d _mm_cmpnlt_sd(__m128d a, __m128d b) __m128d _mm_cmpngt_sd(__m128d a, __m128d b) __m128d _mm_cmpord_sd(__m128d a, __m128d b) __m128d _mm_cmpunord_sd(__m128d a, __m128d b) __m128d _mm_cmpnle_sd(__m128d a, __m128d b) CMPSD for not-greater-than-or-equal __m128d _mm_cmpnge_sd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online