ia-32_instruction-set-ref_a-m

Valid valid compat leg mode valid valid valid valid

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Unformatted text preview: Valid Compat/ Leg Mode Valid Description Classify value or number in ST(0). Description Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below). . Table 3-47. FXAM Results Class Unsupported NaN Normal finite number Infinity Zero Empty Denormal number C3 0 0 0 0 1 1 1 C2 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation C1 sign bit of ST; (* 0 for positive, 1 for negative *) CASE (class of value or number in ST(0)) OF Unsupported:C3, C2, C0 000; NaN: C3, C2, C0 001; Normal: C3, C2, C0 010; Infinity: C3, C2, C0 011; Zero: C3, C2, C0 100; Empty: C3, C2, C0 101; Denormal: C3, C2, C0 110; ESAC; Vol. 2 3-409 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 C0, C2, C3 Sign of value in ST(0). See Table 3-47. Floating-Point Exceptions None. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-410 Vol. 2 INSTRUCTION SET REFERENCE, A-M FXCH--Exchange Register Contents Opcode D9 C8+i D9 C9 Instruction FXCH ST(i) FXCH 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Description Exchange the contents of ST(0) and ST(i). Exchange the contents of ST(0) and ST(1). Description Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged. This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floatingpoint instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack: FXCH ST(3); FSQRT; FXCH ST(3); This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF (Number-of-operands) is 1 THEN temp ST(0); ST(0) SRC; SRC temp; ELSE temp ST(0); ST(0) ST(1); ST(1) temp; FI; FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred; otherwise, set to 1. Undefined. Floating-Point Exceptions #IS Stack underflow occurred. Vol. 2 3-411 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions a...
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