ia-32_instruction-set-ref_a-m

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Unformatted text preview: 0 - SRC 0 +0 SRC + NaN +F - F or 0 DEST DEST +F + NaN + * + + + + + NaN NaN NaN NaN NaN NaN NaN NaN NaN NOTES: F Means finite floating-point value. I Means integer. * Indicates floating-point invalid-arithmetic-operand (#IA) exception. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF Instruction = FIADD THEN DEST DEST + ConvertToDoubleExtendedPrecisionFP(SRC); ELSE (* Source operand is floating-point value *) DEST DEST + SRC; FI; IF Instruction = FADDP THEN PopRegisterStack; FI; Vol. 2 3-289 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined. Floating-Point Exceptions #IS #IA #D #U #O #P Stack underflow occurred. Operand is an SNaN value or unsupported format. Operands are infinities of unlike sign. Source operand is a denormal value. Result is too small for destination format. Result is too large for destination format. Value cannot be represented exactly in destination format. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. 3-290 Vol. 2 INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-291 INSTRUCTION SET REFERENCE, A-M FBLD--Load Binary Coded Decimal Opcode DF /4 Instruction FBLD m80 dec 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert BCD value to floating-point and push onto the FPU stack. Description Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto the FPU stac...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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