ia-32_instruction-set-ref_a-m

Xmm register the two single precision floating point

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: he effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-216 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #MF #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-217 INSTRUCTION SET REFERENCE, A-M CVTSD2SI--Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer Opcode F2 0F 2D /r Instruction CVTSD2SI r32, xmm/m64 CVTSD2SI r64, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer r32. Convert one double-precision floating-point value from xmm/m64 to one signed quadword integer signextended into r64. REX.W + F2 0F 2D /r Valid N.E. Description Converts a double-precision floating-point value in the source operand (second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits. Operation IF 64-Bit Mode and OperandSize = 64 THEN DEST[63:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]); ELSE DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integ...
View Full Document

  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

{[ snackBarMessage ]}

Ask a homework question - tutors are online