ia-32_instruction-set-ref_a-m

A simd floating point exceptions none 3 224 vol 2

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Unformatted text preview: to Scalar Single-Precision Floating-Point Value Opcode F3 0F 2A /r Instruction CVTSI2SS xmm, r/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm. Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm. REX.W + F3 0F 2A /r CVTSI2SS xmm, r/m64 Valid N.E. Description Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the source operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The source operand can be a general-purpose register or a memory location. The destination operand is an XMM register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operands. See the summary chart at the beginning of this section for encoding data and limits. Operation IF 64-Bit Mode And OperandSize = 64 THEN DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]); (* DEST[127:32] unchanged *) ELSE DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]); (* DEST[127:32] unchanged *) FI; Intel C/C++ Compiler Intrinsic Equivalent __m128_mm_cvtsi32_ss(__m128d a, int b) Vol. 2 3-227 INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Precision. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-228 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exception...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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