ia-32_instruction-set-ref_a-m

Above the j bit is defined to be the 1 bit binary

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Unformatted text preview: REFERENCE, A-M exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments). Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If instruction is preceded by a LOCK override prefix. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC For a page fault. For unaligned memory reference. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #MF #PF(fault-code) #NM #UD If there is a pending x87 FPU exception. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If instruction is preceded by a LOCK prefix. 3-424 Vol. 2 INSTRUCTION SET REFERENCE, A-M #AC If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments). Implementation Note The order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both occur on an instruction boundary is given in Table 5-2 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. This order vary for FXSAVE for different processor implementations. Vol. 2 3-425 INSTRUCTION SET REFERENCE, A-M FXTRACT--Extract Exponent and Significand Opcode D9 F4 Instruction FXTRACT 64-Bit Mode Valid Compat/ Leg Mode Valid Description Separate value in ST(0) into exponent and significand, store exponent in ST(0), and push the significand onto the register stack. Descriptio...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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