ia-32_instruction-set-ref_a-m

Address in the ss segment for a page fault if

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Unformatted text preview: tion and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CRO.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. Vol. 2 3-43 INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-44 Vol. 2 INSTRUCTION SET REFERENCE, A-M ADDSUBPD--Packed Double-FP Add/Subtract Opcode 66 0F D0 /r Instruction ADDSUBPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add/subtract double-precision floating-point values from xmm2/m128 to xmm1. Description Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand. Subtracts the double-precision floating-point value in the low quadword of the source operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand. See Figure 3-3. The source operand can be a 128-bit memory location or an XMM register. The destination operand is an XMM register. Figure 3-3. ADDSUBPD--Packed Double-FP Add/Subtract In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15). Vol. 2 3-45 INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] - xmm2/m128[63:0]; xmm1[127:64] = xmm1[127:64] + xmm2/m128[127:64]; Intel C/C++ Compiler Intrinsic Equivalent ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1. If CR0.EM is 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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