Unformatted text preview: The comparison predicate operand is an 8-bit immediate, the first 3 bits of which define the type of comparison to be made (see Table 3-7). Bits 4 through 7 of the immediate are reserved. The unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN. A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate a fault, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN. Some of the comparisons listed in Table 3-7 (such as the greater-than, greater-thanor-equal, not-greater-than, and not-greater-than-or-equal relations) can be made only through software emulation. For these comparisons the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in Table 3-7 under the heading Emulation. Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPS instruction. See Table 3-9. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). 3-130 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-9. Pseudo-Ops and CMPPS
Pseudo-Op CMPEQPS xmm1, xmm2 CMPLTPS xmm1, xmm2 CMPLEPS xmm1, xmm2 CMPUNORDPS xmm1, xmm2 CMPNEQPS xmm1, xmm2 CMPNLTPS xmm1, xmm2 CMPNLEPS xmm1, xmm2 CMPORDPS xmm1, xmm2 Implementation CMPPS xmm1, xmm2, 0 CMPPS xmm1, xmm2, 1 CMPPS xmm1, xmm2, 2 CMPPS xmm1, xmm2, 3 CMPPS xmm1, xmm2, 4 CMPPS xmm1, xmm2, 5 CMPPS xmm1, xmm2, 6 CMPPS xmm1, xmm2, 7 The greater-than relations not implemented by the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.) Operation
CASE (COMPARISON PREDICATE) OF 0: OP EQ; 1: OP LT; 2: OP LE; 3: OP UNORD; 4: OP NE; 5: OP NLT; 6: OP NLE; 7: OP ORD; EASC; CMP0 DEST[31:0] OP SRC[31:0]; CMP1 DEST[63:32] OP SRC[63:32]; CMP2 DEST [95:64] OP SRC[95:64]; CMP3 DEST[127:96] OP SRC[127:96]; IF CMP0 = TRUE THEN DEST[31:0] FFFFFFFFH; ELSE DEST[31:0] 00000000H; FI; IF CMP1 = TRUE THEN DEST[63:32] FFFFFFFFH; ELSE DEST[63:32] 00000000H; FI; IF CMP2 = TRUE Vol. 2 3-131 INSTRUCTION SET REFERENCE, A-M THEN DEST95:64] FFFFFFFFH; ELSE DEST[95:64] 00000000H; FI; IF CMP3 = TRUE THEN DEST[127:96] FFFFFFFFH; ELSE DEST[127:96] 00000000H; FI; Intel C/C++ Compiler Intrinsic Equivalents
CMPPS for equality CMPPS for less-than CMPPS for less-than-or-equal CMPPS for greater-than CMPPS for greater-than-or-equal CMPPS for inequality CMPPS for...
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- Winter '11
- X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values