ia-32_instruction-set-ref_a-m

And debug registers are available the rexr bit is

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Unformatted text preview: xception (#UD). 2-16 Vol. 2 CHAPTER 3 INSTRUCTION SET REFERENCE, A-M This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3, and system instructions. See also Chapter 4, "Instruction Set Reference, N-Z," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B. For each instruction, each operand combination is described. A description of the instruction and its operand, an operational description, a description of the effect of the instructions on flags in the EFLAGS register, and a summary of exceptions that can be generated are also provided. 3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES This section describes the format of information contained in the instruction reference pages in this chapter. It explains notational conventions and abbreviations used in these sections. 3.1.1 Instruction Format The following is an example of the format used for each instruction description in this chapter. The heading below introduces the example. The table below provides an example summary table. CMC--Complement Carry Flag [Example Only] Opcode F5 Instruction CMC 64-bit Mode Valid Compat/ Leg Mode Valid Description Complement carry flag. 3.1.1.1 Opcode Column in the Instruction Summary Table The "Opcode" column in the table above shows the object code produced for each form of the instruction. When possible, codes are given as hexadecimal bytes in the Vol. 2 3-1 INSTRUCTION SET REFERENCE, A-M same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows: REX.W -- Indicates the use of a REX prefix that affects operand size or instruction semantics. The ordering of the REX prefix and other optional/mandatory instruction prefixes are discussed Chapter 2. Note that REX prefixes that promote legacy instructions to 64-bit behavior are not listed explicitly in the opcode column. /digit -- A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode. /r -- Indicates that the ModR/M byte of the instruction contains a register operand and an r/m operand. cb, cw, cd, cp, co, ct -- A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp), 8-byte (co) or 10-byte (ct) value following the opcode. This value is used to specify a code offset and possibly a new value for the code segment register. ib, iw, id, io -- A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte (io) immediate operand to the instruction that follows the opcode, ModR/M bytes or scaleindexing bytes. The opcode determines if the operand is a signed value. All words, doublewords and quadwords are given with the low-order byte first. +rb, +rw, +rd, +ro -- A register code, from 0 through 7, added to the hexadecimal by...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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