ia-32_instruction-set-ref_a-m

And no access rights are loaded in the destination

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Unformatted text preview: tion is a replacement for MOVDQU (load) in situations where cache line splits significantly affect performance. It should not be used in situations where store-load forwarding is performance critical. If performance of store-load forwarding is critical to the application, use MOVDQA store-load pairs when data is 128-bit aligned or MOVDQU store-load pairs when data is 128-bit unaligned. If the memory address is not aligned on 16-byte boundary, some implementations may load up to 32 bytes and return 16 bytes in the destination. Some processor implementations may issue multiple loads to access the appropriate 16 bytes. Developers of multi-threaded or multi-processor software should be aware that on these processors the loads will be performed in a non-atomic way. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation xmm[127:0] = m128; Vol. 2 3-517 INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent LDDQU __m128i _mm_lddqu_si128(__m128i const *p) Numeric Exceptions None. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR4.OSFXSR[bit 9] = 0. If CR0.EM[bit 2] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real Address Mode Exceptions GP(0) #NM #UD If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) #NM #UD If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-518 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) If a page fault occurs. Vol. 2 3-519 INSTRUCTION SET REFERENCE, A-M LDMXCSR--Load MXCSR Register Opcode 0F,AE,/2 Instruction LDMXCSR m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load MXCSR register from m32. Description Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location. See "MXCSR Control and Status Register" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a de...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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