ia-32_instruction-set-ref_a-m

And the destination operand is an xmm register this

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Unformatted text preview: doubleword operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST SRC; Non-64-bit Mode: IF (Byte move) THEN IF DF = 0 THEN (E)SI (E)SI + 1; (E)DI (E)DI + 1; ELSE Vol. 2 3-655 INSTRUCTION SET REFERENCE, A-M (E)SI (E)SI 1; (E)DI (E)DI 1; FI; ELSE IF (Word move) THEN IF DF = 0 (E)SI (E)SI + 2; (E)DI (E)DI + 2; FI; ELSE (E)SI (E)SI 2; (E)DI (E)DI 2; FI; ELSE IF (Doubleword move) THEN IF DF = 0 (E)SI (E)SI + 4; (E)DI (E)DI + 4; FI; ELSE (E)SI (E)SI 4; (E)DI (E)DI 4; FI; FI; 64-bit Mode: IF (Byte move) THEN IF DF = 0 THEN (R|E)SI (R|E)SI + 1; (R|E)DI (R|E)DI + 1; ELSE (R|E)SI (R|E)SI 1; (R|E)DI (R|E)DI 1; FI; ELSE IF (Word move) THEN IF DF = 0 (R|E)SI (R|E)SI + 2; (R|E)DI (R|E)DI + 2; FI; ELSE (R|E)SI (R|E)SI 2; (R|E)DI (R|E)DI 2; FI; ELSE IF (Doubleword move) THEN IF DF = 0 3-656 Vol. 2 INSTRUCTION SET REFERENCE, A-M (R|E)SI (R|E)SI + 4; (R|E)DI (R|E)DI + 4; FI; ELSE (R|E)SI (R|E)SI 4; (R|E)DI (R|E)DI 4; FI; ELSE IF (Quadword move) THEN IF DF = 0 (R|E)SI (R|E)SI + 8; (R|E)DI (R|E)DI + 8; FI; ELSE (R|E)SI (R|E)SI 8; (R|E)DI (R|E)DI 8; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. Vol. 2 3-657 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-658 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVSD--Move Scalar Double-Precision Floating-Point Value Opcode F2 0F 10 /r F2 0F 11 /r Instruction MOVSD xmm1, xmm2/m64 MOVSD xmm2/m64, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move scalar double-precision floating-point value from xmm2/m64 to xmm1 register. Move scalar double-precision floating-point value from xmm1 register to xmm2/m64. Valid Valid D...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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