ia-32_instruction-set-ref_a-m

As in protected mode 64 bit mode exceptions same

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Unformatted text preview: and limits. Operation DEST SRC; Intel C/C++ Compiler Intrinsic Equivalent MOVNTDQ void_mm_stream_si32 (int *p, int a) Vol. 2 3-639 INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #UD If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #UD #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CPUID.01H:EDX.SSE2[bit 26] = 0. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-640 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVNTPD--Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F 2B /r Instruction MOVNTPD m128, xmm Description Move packed double-precision floating-point values from xmm to m128 using non-temporal hint. Description Moves the double quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is an XMM register, which is assumed to contain two packed double-precision floating-point values. The destination operand is a 128-bit memory location. The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see "Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1. Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors might use different memory types to read/write the destination memory locations. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (X...
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