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Unformatted text preview: bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-614 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVDQU--Move Unaligned Double Quadword
Opcode F3 0F 6F /r Instruction MOVDQU xmm1, xmm2/m128 MOVDQU xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move unaligned double quadword from xmm2/m128 to xmm1. Move unaligned double quadword from xmm1 to xmm2/m128. F3 0F 7F /r Valid Valid Description
Moves a double quadword from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte boundary without causing a general-protection exception (#GP) to be generated. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the MOVDQA instruction. While executing in 16-bit addressing mode, a linear address for a 128-bit data access that overlaps the end of a 16-bit segment is not allowed and is defined as reserved behavior. A specific processor implementation may or may not generate a generalprotection exception (#GP) in this situation, and the address that spans the end of the segment may or may not wrap around to the beginning of the segment. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
DEST SRC; Intel C/C++ Compiler Intrinsic Equivalent
MOVDQU MOVDQU void _mm_storeu_si128 ( __m128i *p, __m128i a) __m128i _mm_loadu_si128 ( __m128i *p) SIMD Floating-Point Exceptions
None. Vol. 2 3-615 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions
#GP(0) #SS(0) #NM #UD If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #PF(fault-code) If a page fault occurs. Real-Address Mode Exceptions
#GP(0) #NM #UD If any part of the operand lies outside of the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
#SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-616 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVDQ2Q--Move Quadword from XMM to MMX Technology Register
64-Bit Mode Valid Compat...
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- Winter '11