ia-32_instruction-set-ref_a-m

Data between memory locations when the source and

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Unformatted text preview: ault-code) #NM #UD For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.SSE3(ECX, bit 0) is 0. 3-664 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVSLDUP--Move Packed Single-FP Low and Duplicate 64Bit Mode Valid Compat/ Leg Mode Valid Opcode F3 0F 12 /r Instruction MOVSLDUP xmm1, xmm2/m128 Description Move two single-precision floatingpoint values from the lower 32-bit operand of each qword in xmm2/m128 to xmm1 and duplicate each 32-bit operand to the higher 32bits of each qword. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data. When a memory address is indicated, the 16 bytes of data at memory location m128 are loaded and the single-precision elements in positions 0 and 2 are duplicated. When the register-register form of this operation is used, the same operation is performed but with data coming from the 128-bit source register. See Figure 3-16. Figure 3-16. MOVSLDUP--Move Packed Single-FP Low and Duplicate In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Vol. 2 3-665 INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[31:0]; xmm1[63:32] = m128[31:0]; xmm1[95:64] = m128[95:64]; xmm1[127:96] = m128[95::64]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[31:0]; xmm1[63:32] = xmm2[31:0]; xmm1[95:64] = xmm2[95:64]; xmm1[127:96] = xmm2[95:64]; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVSLDUP __m128 _mm_moveldup_ps(__m128 a) Exceptions General protection exception if not aligned on 16-byte boundary, regardless of segment. Numeric Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. 3-666 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #UD If CR0.TS[bit 3] = 1.If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical fo...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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