ia-32_instruction-set-ref_a-m

Descriptions vol 2 3 9 instruction set reference

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Unformatted text preview: nted by the saturated value 255 (FFH). SaturateToUnsignedWord -- Represents the result of an operation as a signed 16-bit value. If the result is less than zero it is represented by the saturated value zero (00H); if it is greater than 65535, it is represented by the saturated value 65535 (FFFFH). LowOrderWord(DEST * SRC) -- Multiplies a word operand by a word operand and stores the least significant word of the doubleword result in the destination operand. HighOrderWord(DEST * SRC) -- Multiplies a word operand by a word operand and stores the most significant word of the doubleword result in the destination operand. Push(value) -- Pushes a value onto the stack. The number of bytes pushed is determined by the operand-size attribute of the instruction. See the "Operation" subsection of the "PUSH--Push Word, Doubleword or Quadword Onto the Stack" section in Chapter 4 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B. Pop() removes the value from the top of the stack and returns it. The statement EAX Pop(); assigns to EAX the 32-bit value from the top of the stack. Pop will return either a word, a doubleword or a quadword depending on the operand-size attribute. See the "Operation" subsection in the "POP--Pop a Value from the Stack" section of Chapter 4 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B. PopRegisterStack -- Marks the FPU ST(0) register as empty and increments the FPU register stack pointer (TOP) by 1. Switch-Tasks -- Performs a task switch. Bit(BitBase, BitOffset) -- Returns the value of a bit within a bit string. The bit string is a sequence of bits in memory or a register. Bits are numbered from loworder to high-order within registers and within memory bytes. If the BitBase is a register, the BitOffset can be in the range 0 to [15, 31, 63] depending on the mode and register size. See Figure 3-1: the function Bit[RAX, 21] is illustrated. 3-10 Vol. 2 INSTRUCTION SET REFERENCE, A-M 63 31 21 0 Bit Offset 21 Figure 3-1. Bit Offset for BIT[RAX, 21] If BitBase is a memory address, the BitOffset can range has different ranges depending on the operand size (see Table 3-2). Table 3-2. Range of Bit Positions Specified by Bit Offset Operands Operand Size 16 32 64 Immediate BitOffset 0 to 15 0 to 31 0 to 63 Register BitOffset -215 to 215 - 1 -231 to 231 - 1 -263 to 263 - 1 The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where DIV is signed division with rounding towards negative infinity and MOD returns a positive number (see Figure 3-2). 7 5 0 7 0 7 0 BitBase + BitBase BitBase - BitOffset +13 7 0 7 0 7 5 0 BitBase BitBase - BitBase - BitOffset - Figure 3-2. Memory Bit Indexing Vol. 2 3-11 INSTRUCTION SET REFERENCE, A-M 3.1.1.8 Intel C/C++ Compiler Intrinsics Equivalents Section The Intel C/C++ compiler intrinsics equivalents are special C/C++ coding extensions that allow using the syntax of C fun...
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