ia-32_instruction-set-ref_a-m

Division 3 318 vol 2 instruction set reference a m if

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Unformatted text preview: 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-321 INSTRUCTION SET REFERENCE, A-M FFREE--Free Floating-Point Register Opcode DD C0+i Instruction FFREE ST(i) 64-Bit Mode Valid Compat/ Leg Mode Valid Description Sets tag for ST(i) to empty. Description Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation TAG(i) 11B; FPU Flags Affected C0, C1, C2, C3 undefined. Floating-Point Exceptions None. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-322 Vol. 2 INSTRUCTION SET REFERENCE, A-M FICOM/FICOMP--Compare Integer Opcode DE /2 DA /2 DE /3 DA /3 Instruction FICOM m16int FICOM m32int FICOMP m16int FICOMP m32int 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Description Compare ST(0) with m16int. Compare ST(0) with m32int. Compare ST(0) with m16int and pop stack register. Compare ST(0) with m32int and pop stack register. Description Compares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). The integer value is converted to double extended-precision floating-point format before the comparison is made. Table 3-31. FICOM/FICOMP Results Condition ST(0) > SRC ST(0) < SRC ST(0) = SRC Unordered C3 0 0 1 1 C2 0 0 0 1 C0 0 1 0 1 These instructions perform an "unordered comparison." An unordered comparison also checks the class of the numbers being compared (see "FXAM--ExamineModR/M" in this chapter). If either operand is a NaN or is in an undefined format, the condition flags are set to "unordered." The sign of zero is ignored, so that 0.0 +0.0. The FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor marks the ST(0) register empty and increments the stack pointer (TOP) by 1. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation CASE (relation of operands)...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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