ia-32_instruction-set-ref_a-m

Error exception mf vector number 16 being generated

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Unformatted text preview: ing-point denormal operand Floating-point numeric overflow Floating-point numeric underflow Floating-point inexact result (precision) Source - x87 FPU stack overflow or underflow - Invalid FPU arithmetic operation Divide-by-zero Source operand that is a denormal number Overflow in result Underflow in result Inexact result (precision) 3.1.1.15 SIMD Floating-Point Exceptions Section The "SIMD Floating-Point Exceptions" section lists exceptions that can occur when an SSE/SSE2/SSE3 floating-point instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XM, vector number 19) being generated. Table 3-5 associates a one-letter mnemonic with the corresponding exception name. For a detailed description of these exceptions, refer to "SSE and SSE2 Exceptions", in Chapter 11 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1. Table 3-5. SIMD Floating-Point Exceptions Mnemonic #I #Z #D #O #U #P Name Floating-point invalid operation Floating-point divide-by-zero Floating-point denormal operand Floating-point numeric overflow Floating-point inexact result Divide-by-zero Source operand that is a denormal number Overflow in result Inexact result (precision) Source Invalid arithmetic operation or source operand Floating-point numeric underflow Underflow in result Vol. 2 3-17 INSTRUCTION SET REFERENCE, A-M 3.1.1.16 Compatibility Mode Exceptions Section This section lists exception that occur within compatibility mode. 3.1.1.17 64-Bit Mode Exceptions Section This section lists exception that occur within 64-bit mode. 3.2 INSTRUCTIONS (A-M) The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-M). See also: Chapter 4, "Instruction Set Reference, N-Z," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B. 3-18 Vol. 2 INSTRUCTION SET REFERENCE, A-M AAA--ASCII Adjust After Addition Opcode 37 Instruction AAA 64-Bit Mode Invalid Compat/ Leg Mode Valid Description ASCII adjust AL after addition. Description Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result. If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are set to 0. This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode. Operation IF 64-Bit Mode THEN #UD; ELSE IF ((AL AND 0FH) > 9) or (AF = 1) THEN AL AL + 6;...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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