ia-32_instruction-set-ref_a-m

Exception any subsequent reference to a segment whose

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Unformatted text preview: de while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. Vol. 2 3-525 INSTRUCTION SET REFERENCE, A-M #SS #UD If a memory operand effective address is outside the SS segment limit. If source operand is not a memory location. Virtual-8086 Mode Exceptions #UD #GP(0) #SS(0) #PF(fault-code) #AC(0) If source operand is not a memory location. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. If a NULL selector is attempted to be loaded into the SS register in compatibility mode. If a NULL selector is attempted to be loaded into the SS register in CPL3 and 64-bit mode. If a NULL selector is attempted to be loaded into the SS register in non-CPL3 and 64-bit mode where its RPL is not equal to CPL. #GP(Selector) If the FS, or GS register is being loaded with a non-NULL segment selector and any of the following is true: the segment selector index is not within descriptor table limits, the memory address of the descriptor is non-canonical, the segment is neither a data nor a readable code segment, or the segment is a data or nonconforming-code segment and both RPL and CPL are greater than DPL. If the SS register is being loaded and any of the following is true: the segment selector index is not within the descriptor table limits, the memory address of the descriptor is non-canonical, the segment selector RPL is not equal to CPL, the segment is a nonwritable data segment, or DPL is not equal to CPL. #SS(0) #SS(Selector) #NP(selector) If a memory operand effective address is non-canonical If the SS register is being loaded and the segment is marked not present. If FS, or GS register is being loaded with a non-NULL segment selector and the segment is marked not present. 3-526 Vol. 2 INSTRUCTION SET REFERENCE, A-M #PF(fault-code) #AC(0) #UD If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. If source operand is not a memory location. Vol. 2 3-527 INSTRUCTION SET REFERENCE, A-M LEA--Load Effective Address Opcode 8D /r 8D /r REX.W + 8D /r Instruction LEA r16,m LEA r32,m LEA r64,m 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description Store effective address for m in register r16. Store effective address for m in register r32. Store effective address for m in register r64. Description Computes the effective address of the second operand (the source operand) and stores it in the first operand (destination operand). The source operand is a memory address (offset part) specified with one of the processors addre...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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