ia-32_instruction-set-ref_a-m

Exceptions as in protected mode 64 bit mode

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Unformatted text preview: tected Mode. 3-608 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If CR0.EM[bit 2] = 1. (XMM register operations only) if CR4.OSFXSR[bit 9] = 0. (XMM register operations only) if CPUID.01H:EDX.SSE2[bit 26] = 0. #NM #MF #PF(fault-code) #AC(0) If CR0.TS[bit 3] = 1. (MMX register operations only) If there is a pending FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-609 INSTRUCTION SET REFERENCE, A-M MOVDDUP--Move One Double-FP and Duplicate Opcode F2 0F 12 /r Instruction MOVDDUP xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move one double-precision floatingpoint value from the lower 64-bit operand in xmm2/m64 to xmm1 and duplicate. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data. When a memory address is indicated, the 8 bytes of data at memory location m64 are loaded. When the register-register form of this operation is used, the lower half of the 128-bit source register is duplicated and copied into the 128-bit destination register. See Figure 3-14. Figure 3-14. MOVDDUP--Move One Double-FP and Duplicate In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). 3-610 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m64) THEN (* Load instruction *) xmm1[63:0] = m64; xmm1[127:64] = m64; ELSE (* Move instruction *) xmm1[63:0] = xmm2[63:0]; xmm1[127:64] = xmm2[63:0]; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVDDUP __m128d _mm_movedup_pd(__m128d a) __m128d _mm_loaddup_pd(double const * dp) Exceptions None Numeric Exceptions None Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-611 INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) #NM #UD If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) #NM #UD If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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