ia-32_instruction-set-ref_a-m

Extended function information if a value is entered

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Unformatted text preview: size in bytes) Bits 23-16: Maximum number of logical processors in this physical package. Bits 31-24: Initial APIC ID Extended Feature Information (see Figure 3-6 and Table 3-15) Feature Information (see Figure 3-7 and Table 3-16) Cache and TLB Information (see Table 3-17) Cache and TLB Information Cache and TLB Information Cache and TLB Information 01H ECX EDX 02H EAX EBX ECX EDX Vol. 2 3-161 INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 03H EAX EBX ECX EDX Information Provided about the Processor Reserved. Reserved. Bits 00-31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.) Bits 32-63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.) NOTE: Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned using CPUID) to check for PSN support before accessing the feature. See AP485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) for more information on PSN. CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default). Deterministic Cache Parameters Leaf 3-162 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 04H NOTE: 04H output depends on the initial value in ECX. See also: "INPUT EAX = 4: Returns Deterministic Cache Parameters for each level on page 3-180. Bits 4-0: Cache Type* Bits 7-5: Cache Level (starts at 1) Bits 8: Self Initializing cache level (does not need SW initialization) Bits 9: Fully Associative cache Bits 13-10: Reserved Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)** Bits 31-26: Maximum number of processor cores in the physical package. **, *** Bits 11-00: L = System Coherency Line Size** Bits 21-12: P = Physical Line partitions** Bits 31-22: W = Ways of associativity** Bits 31-00: S = Number of Sets** Reserved = 0 NOTES: * Cache Type fields: 0 = Null - No more caches 1 = Data Cache 2 = Instruction Cache Information Provided about the Processor EAX EBX ECX EDX 3 = Unified Cache 4-31 = Reserved ** Add one to the return value to get the result. *** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0. MONITOR/MWAIT Leaf Vol. 2 3-163 INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 5H EAX Information Provided about the Processor Bits 15-00: Smallest monitor-line size in bytes (default is processor's monitor granularity) Bits 31-16: Reserved = 0 Bits 15-00: Largest monitor-line size in bytes (default is processor's monitor granularity) Bits 31-16: Reserved = 0 Bits 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported Bits 01: Suppor...
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