Flags in the eflags register according to the results

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Unformatted text preview: before the compare string instruction is executed. The no-operands form provides "short forms" of the byte, word, and doubleword versions of the CMPS instructions. Here also the DS:(E)SI (or RSI) and ES:(E)DI (or Vol. 2 3-135 INSTRUCTION SET REFERENCE, A-M RDI) registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using REX.W). After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the DF flag is 1, the registers decrement.) The registers increment or decrement by 1 for byte operations, by 2 for word operations, 4 for doubleword operations. If operand size is 64, RSI and RDI registers increment by 8 for quadword operations. The CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the REP prefix for block comparisons. More often, however, these instructions will be used in a LOOP construct that takes some action based on the setting of the status flags before the next comparison is made. See "REP/REPE/REPZ/REPNE/REPNZ--Repeat String Operation Prefix" in Chapter 4, in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B, for a description of the REP prefix. In 64-bit mode, the instruction's default address size is 64 bits, 32 bit address size is supported using the prefix 67H. Use of the REX.W prefix promotes doubleword operation to 64 bits (see CMPSQ). See the summary chart at the beginning of this section for encoding data and limits. Operation temp SRC1 - SRC2; SetStatusFlags(temp); IF (64-Bit Mode) THEN IF (Byte comparison) THEN IF DF = 0 THEN (R|E)SI (R|E)SI + 1; (R|E)DI (R|E)DI + 1; ELSE (R|E)SI (R|E)SI 1; (R|E)DI (R|E)DI 1; FI; ELSE IF (Word comparison) THEN IF DF = 0 THEN (R|E)SI (R|E)SI + 2; (R|E)DI (R|E)DI + 2; ELSE 3-136 Vol. 2 INSTRUCTION SET REFERENCE, A-M (R|E)SI (R|E)SI 2; (R|E)DI (R|E)DI 2; FI; ELSE IF (Doubleword comparison) THEN IF DF = 0 THEN (R|E)SI (R|E)SI + 4; (R|E)DI (R|E)DI + 4; ELSE (R|E)SI (R|E)SI 4; (R|E)DI (R|E)DI 4; FI; ELSE (* Quadword comparison *) THEN IF DF = 0 (R|E)SI (R|E)SI + 8; (R|E)DI (R|E)DI + 8; ELSE (R|E)SI (R|E)SI 8; (R|E)DI (R|E)DI 8; FI; FI; ELSE (* Non-64-bit Mode *) IF (byte comparison) THEN IF DF = 0 THEN (E)SI (E)SI + 1; (E)DI (E)DI + 1; ELSE (E)SI (E)SI 1; (E)DI (E)DI 1; FI; ELSE IF (Word comparison) THEN IF DF = 0 (E)SI (E)SI + 2; (E)DI (E)DI + 2; ELSE (E)SI (E)SI 2; (E)DI (E)DI 2; FI; ELSE (* Doubleword comparison *) THEN IF DF = 0 (E)SI (E)SI + 4; (E)DI (E)DI + 4; Vol. 2 3-137 INSTRUCTION SET REFERENCE, A-M ELSE (E)SI (E)SI 4; (E)DI (E)DI 4; FI; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison. Prote...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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