ia-32_instruction-set-ref_a-m

Floating point divide instructions always results in

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Unformatted text preview: or CR0.TS[bit 3] = 1. 3-316 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-317 INSTRUCTION SET REFERENCE, A-M FDIVR/FDIVRP/FIDIVR--Reverse Divide Opcode D8 /7 DC /7 D8 F8+i DC F0+i DE F0+i DE F1 DA /7 DE /7 Instruction FDIVR m32fp FDIVR m64fp FDIVR ST(0), ST(i) FDIVR ST(i), ST(0) FDIVRP ST(i), ST(0) FDIVRP FIDIVR m32int FIDIVR m16int 64Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Description Divide m32fp by ST(0) and store result in ST(0). Divide m64fp by ST(0) and store result in ST(0). Divide ST(i) by ST(0) and store result in ST(0). Divide ST(0) by ST(i) and store result in ST(i). Divide ST(0) by ST(i), store result in ST(i), and pop the register stack. Divide ST(0) by ST(1), store result in ST(1), and pop the register stack. Divide m32int by ST(0) and store result in ST(0). Divide m16int by ST(0) and store result in ST(0). Description Divides the source operand by the destination operand and stores the result in the destination location. The destination operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format. These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to support more efficient coding. The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1) register. The one-operand version divides the contents of a memory location (either a floating-point or an integer value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by the contents of the ST(0) register or vice versa. The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point divide instructions always results in the re...
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