Unformatted text preview: vided by the SSE, SSE2, SSE3, and MMX technology when writing programs with the intrinsics. Keep the following important issues in mind: Certain intrinsics, such as _mm_loadr_ps and _mm_cmpgt_ss, are not directly supported by the instruction set. While these intrinsics are convenient programming aids, be mindful of their implementation cost. Data loaded or stored as __m128 objects must generally be 16-byte-aligned. Some intrinsics require that their argument be immediates, that is, constant integers (literals), due to the nature of the instruction. The result of arithmetic operations acting on two NaN (Not a Number) arguments is undefined. Therefore, floating-point operations using NaN arguments may not match the expected behavior of the corresponding assembly instructions. For a more detailed description of each intrinsic and additional information related to its usage, refer to Intel C/C++ compiler documentation. See: -- http://www.intel.com/support/performancetools/ -- Appendix C, "Intel C/C++ Compiler Intrinsics and Functional Equivalents," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2B, for more information on using intrinsics. 126.96.36.199 Flags Affected Section The "Flags Affected" section lists the flags in the EFLAGS register that are affected by the instruction. When a flag is cleared, it is equal to 0; when it is set, it is equal to 1. The arithmetic and logical instructions usually assign values to the status flags in a uniform manner (see Appendix A, "Eflags Cross-Reference," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1). Non-conventional 3-14 Vol. 2 INSTRUCTION SET REFERENCE, A-M assignments are described in the "Operation" section. The values of flags listed as undefined may be changed by the instruction in an indeterminate manner. Flags that are not listed are unchanged by the instruction. 188.8.131.52 FPU Flags Affected Section The floating-point instructions have an "FPU Flags Affected" section that describes how each instruction can affect the four condition code flags of the FPU status word. 184.108.40.206 Protected Mode Exceptions Section The "Protected Mode Exceptions" section lists the exceptions that can occur when the instruction is executed in protected mode and the reasons for the exceptions. Each exception is given a mnemonic that consists of a pound sign (#) followed by two letters and an optional error code in parentheses. For example, #GP(0) denotes a general protection exception with an error code of 0. Table 3-3 associates each twoletter mnemonic with the corresponding interrupt vector number and exception name. See Chapter 5, "Interrupt and Exception Handling," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a detailed description of the exceptions. Application programmers should consult the documentation provided with their operating systems to determine the actio...
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- Winter '11
- X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values