ia-32_instruction-set-ref_a-m

Form if the memory address is in a non canonical form

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Unformatted text preview: bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #AC(0) GP(0) #NM #UD If alignment checking is enabled and an unaligned memory reference is made. If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #AC(0) #SS(0) #GP(0) #PF(fault-code) #NM If alignment checking is enabled and an unaligned memory reference is made. If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. Vol. 2 3-677 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. 3-678 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVZX--Move with Zero-Extend 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Valid N.E. Opcode 0F B6 /r 0F B6 /r REX.W + 0F B6 /r 0F B7 /r REX.W + 0F B7 /r Instruction MOVZX r16, r/m8 MOVZX r32, r/m8 MOVZX r64, r/m8* MOVZX r32, r/m16 MOVZX r64, r/m32 Description Move byte to word with zeroextension. Move byte to doubleword, zero-extension. Move byte to quadword, zero-extension. Move word to doubleword, zero-extension. Move doubleword to quadword, zero-extension. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Copies the contents of the source operand (register or memory location) to the destination operand (register) and zero extends the value to 16 or 32 bits. The size of the converted value depends on the operand-size attribute. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST ZeroExtend(SRC); Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. Vol. 2 3-679 INSTRUCTION SET REFERENCE, A-M #PF(fault-code) #AC(0) If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effect...
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