ia-32_instruction-set-ref_a-m

Gate descriptor types are given in the following

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Unformatted text preview: Descriptor(busy) 1; (* Locked read-modify-write operation on the entire descriptor when setting busy flag *) TaskRegister(SegmentSelector) SRC; TaskRegister(SegmentDescriptor) TSSSegmentDescriptor; 3-554 Vol. 2 INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the source operand contains a NULL segment selector. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already busy. If the selector points to LDT or is beyond the GDT limit. #NP(selector) #SS(0) #PF(fault-code) If the TSS is marked not present. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. Real-Address Mode Exceptions #UD The LTR instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The LTR instruction is not recognized in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the current privilege level is not 0. If the memory address is in a non-canonical form. If the source operand contains a NULL segment selector. #GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already busy. If the selector points to LDT or is beyond the GDT limit. If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero. Vol. 2 3-555 INSTRUCTION SET REFERENCE, A-M #NP(selector) #PF(fault-code) If the TSS is marked not present. If a page fault occurs. 3-556 Vol. 2 INSTRUCTION SET REFERENCE, A-M MASKMOVDQU--Store Selected Bytes of Double Quadword Opcode 66 0F F7 /r Instruction MASKMOVDQU xmm1, xmm2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Selectively write bytes from xmm1 to memory location using the byte mask in xmm2. The default memory location is specified by DS:EDI. Description Stores selected bytes from the source operand (first operand) into an 128-bit memory location. The mask operand (second operand) selects which bytes from the source operand are written to memory. The source and mask operands are XMM registers. The location of the first byte of the memory location is specified by DI/EDI and DS registers. The memory location does not need to be aligned on a natural boundary. (The size of the store address depends on the address-size attribute.) The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write. The MASKMOVEDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-temporal hi...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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