ia-32_instruction-set-ref_a-m

Generates a non temporal hint to the processor to

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Unformatted text preview: ter or a 128-bit memory location. The destination operand is an XMM register. If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is forwarded unchanged to the destination (that is, a QNaN version of the SNaN is not returned). If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] IF ((DEST[63:0] = 0.0) and (SRC[63:0] = 0.0)) THEN SRC[63:0]; ELSE IF (DEST[63:0] = SNaN) THEN SRC[63:0]; FI; ELSE IF SRC[63:0] = SNaN) THEN SRC[63:0]; FI; ELSE IF (DEST[63:0] > SRC[63:0]) THEN DEST[63:0]; ELSE SRC[63:0]; FI; FI; IF ((DEST[127:64] = 0.0) and (SRC[127:64] = 0.0)) THEN SRC[127:64]; ELSE IF (DEST[127:64] = SNaN) THEN SRC[127:64]; FI; ELSE IF SRC[127:64] = SNaN) THEN SRC[127:64]; FI; ELSE IF (DEST[127:64] > SRC[63:0]) DEST[127:64] Vol. 2 3-563 INSTRUCTION SET REFERENCE, A-M THEN DEST[127:64]; ELSE SRC[127:64]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent MAXPD __m128d _mm_max_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD If a memory operand effective address is outside the SS segment limit. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #XM #UD If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-564 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. I...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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