ia-32_instruction-set-ref_a-m

In opcode byte rexx rexr not used

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Unformatted text preview: . . . . 2-12 CONTENTS PAGE Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. Figure A-1. Figure B-1. Bit Offset for BIT[RAX, 21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 Memory Bit Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 ADDSUBPD--Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45 ADDSUBPS--Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-48 Version Information Returned by CPUID in EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-169 Extended Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . 3-171 Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173 Determination of Support for the Processor Brand String. . . . . . . . . . . . . . . . . . . . 3-181 Algorithm for Extracting Maximum Processor Frequency . . . . . . . . . . . . . . . . . . . . 3-183 HADDPD--Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-432 HADDPS--Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435 HSUBPD--Packed Double-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-441 HSUBPS--Packed Single-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-445 MOVDDUP--Move One Double-FP and Duplicate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-610 MOVSHDUP--Move Packed Single-FP High and Duplicate . . . . . . . . . . . . . . . . . . . . 3-662 MOVSLDUP--Move Packed Single-FP Low and Duplicate . . . . . . . . . . . . . . . . . . . . . 3-665 Operation of the PACKSSDW Instruction Using 64-bit Operands. . . . . . . . . . . . . . . .4-26 PMADDWD Execution Model Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . .4-92 PMULHUW and PMULHW Instruction Operation Using 64-bit Operands . . . . . . . 4-113 PMULLU Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . 4-120 PSADBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . 4-146 PSHUB with 64-Bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-150 PSHUFD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152 PSLLW, PSLLD, and PSLLQ Instruction Operation Us...
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