In register st1 divided by the source operand in

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Unformatted text preview: -Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-356 Vol. 2 INSTRUCTION SET REFERENCE, A-M FPREM--Partial Remainder Opcode D9 F8 Instructio n FPREM 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1). Description Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following value: Remainder ST(0) - (Q ST(1)) Here, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)] toward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is less than that of the modulus, unless a partial remainder was computed (as described below). This instruction produces an exact result; the inexact-result exception does not occur and the rounding control has no effect. The following table shows the results obtained when computing the remainder of various classes of numbers, assuming that underflow does not occur. Table 3-36. FPREM Results ST(1) - - -F * -F or -0 -0 +0 +F or +0 * NaN -0 * ** * * ** * NaN +0 * ** * * ** * NaN +F * -F or -0 -0 +0 +F or +0 * NaN + * ST(0) -0 +0 ST(0) * NaN NaN NaN NaN NaN NaN NaN NaN NaN * ST(0) -0 +0 ST(0) * NaN ST(0) -F -0 +0 +F + NaN NOTES: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand (#IA) exception. ** Indicates floating-point zero-divide (#Z) exception. When the result is 0, its sign is the same as that of the dividend. When the modulus is , the result is equal to the value in ST(0). Vol. 2 3-357 INSTRUCTION SET REFERENCE, A-M The FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel 8087 and Intel287 math coprocessors. The FPREM instruction gets its name "partial remainder" because of the way it computes the remainder. This instruction arrives at a remainder through iterative subtraction. It can, however, reduce the exponent of ST(0) by no more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that is less than the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder. The exponent of the partial remainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the instruction (using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing such a...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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