ia-32_instruction-set-ref_a-m

In the destination operand the destination operand

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Unformatted text preview: the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result. The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST DEST + SRC + CF; Flags Affected The OF, SF, ZF, AF, CF, and PF flags are set according to the result. 3-28 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-29 INSTRUCTION SET REFERENCE, A-M ADD--Add Opcode 04 ib 05 iw 05 id REX.W + 05 id Instruction ADD AL, imm8 ADD AX, imm16 ADD EAX, imm32 ADD RAX, imm32 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. Description Add imm8 to AL. Add imm16 to AX. Add imm32 to EAX. Add imm32 signextended to 64-bits to RAX. Add imm8 to r/m8. Add sign-extended imm8 to r/m64. Add imm16 to r/m16. Add imm32 to r/m32. Add imm32 signextended to 64-bits to r/m64. Add sign-extended imm8 to r/m16. Add sign-extended imm8 to r/m32. Add sign-extended imm8 to r/m64. Add r8 to r/m8. Add r8 to r/m8. Add r16 to r/m16. Add r32 to r/m32. Add r64 to r/m64. Add r/m8 to r8. Add r/m8 to r8. Add r/m16 to r16. Add r/m32 to r32. Add r/m64 to r64....
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