ia-32_instruction-set-ref_a-m

Instruction for xmm to memory move dest src12764 intel

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Unformatted text preview: rmits this instruction to access additional registers (XMM8-XMM15). Operation DEST[127:64] SRC[63:0]; (* DEST[63:0] unchanged *) Intel C/C++ Compiler Intrinsic Equivalent MOVHLPS __m128 _mm_movelh_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real Address Mode Exceptions Same exceptions as in Protected Mode. Virtual 8086 Mode Exceptions Same exceptions as in Protected Mode. 3-626 Vol. 2 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-627 INSTRUCTION SET REFERENCE, A-M MOVLPD--Move Low Packed Double-Precision Floating-Point Value 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F 12 /r 66 0F 13 /r Instruction MOVLPD xmm, m64 MOVLPD m64, xmm Valid Valid Description Move double-precision floating-point value from m64 to low quadword of xmm register. Move double-precision floating-point nvalue from low quadword of xmm register to m64. Description Moves a double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be an XMM register or a 64-bit memory location. This instruction allows a double-precision floating-point value to be moved to and from the low quadword of an XMM register and memory. It cannot be used for register to register or memory to memory moves. When the destination operand is an XMM register, the high quadword of the register remains unchanged. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation MOVLPD instruction for memory to XMM move: DEST[63:0] SRC; (* DEST[127:64] unchanged *) MOVLPD instruction for XMM to memory move: DEST SRC[63:0]; Intel C/C++ Compiler Intrinsic Equivalent MOVLPD MOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p) void _mm_storel_pd (double *p, __m128d a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. 3-628 Vol. 2 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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