ia-32_instruction-set-ref_a-m

Instructions operation is the same in non 64 bit

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Unformatted text preview: value's identity as a 0, , or NaN. 3-384 Vol. 2 INSTRUCTION SET REFERENCE, A-M If the destination operand is a non-empty register, the invalid-operation exception is not generated. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation DEST ST(0); IF Instruction = FSTP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0 not roundup; 1 roundup. C0, C2, C3 Undefined. Floating-Point Exceptions #IS #IA Stack underflow occurred. Source operand is an SNaN value or unsupported format. Does not occur if the source operand is in double extended-precision floating-point format. Result is too small for the destination format. Result is too large for the destination format. Value cannot be represented exactly in destination format. #U #O #P Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-385 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-386 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSTCW/FNSTCW--Store x87 FPU Control Word Opcode 9B D9 /7 Instruction FSTCW m2byte FNSTCW* m2byte 64Bit Mode Valid Compat/ Leg Mode Valid Description Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions. Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions. D9 /7 Valid Valid NOTES: * See IA-32...
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