ia-32_instruction-set-ref_a-m

Is a pending x87 fpu exception if cr0embit 2 1 if

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]); DEST[63:32] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]); (* High quadword of destination unchanged *) Intel C/C++ Compiler Intrinsic Equivalent CVTPI2PS __m128 _mm_cvtpi32_ps(__m128 a, __m64 b) SIMD Floating-Point Exceptions Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. 3-206 Vol. 2 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #MF #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #MF #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. Vol. 2 3-207 INSTRUCTION SET REFERENCE, A-M #GP(0) #PF(fault-code) #NM #MF #XM #UD If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-208 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTPS2DQ--Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F 5B /r Instruction CVTPS2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Descr...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online